On Tue, 13 Sep 2022 06:18:10 +0000, Zong Li wrote: > Since composable cache may be L3 cache if private L2 cache exists, we > should use its original name "composable cache" to prevent confusion. > > This patchset contains the modification which is related to ccache, such > as DT binding and EDAC driver. > > The DT binding is based on top of Conor's patch, it has got ready for > merging, and it looks that it would be taken into the next few 6.0-rc > version. If there is any change, the next version of this series will be > posted as well. > https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@xxxxxxxxxxx/ > > [...] Applied, thanks! [1/7] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache https://git.kernel.org/palmer/c/44dce4b084f8 [2/7] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. https://git.kernel.org/palmer/c/ca120a79cf5a [3/7] soc: sifive: ccache: determine the cache level from dts https://git.kernel.org/palmer/c/95f196f3212b [4/7] soc: sifive: ccache: reduce printing on init https://git.kernel.org/palmer/c/3fb787e5bad5 [5/7] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes https://git.kernel.org/palmer/c/696ab9bda22a [6/7] soc: sifive: ccache: define the macro for the register shifts https://git.kernel.org/palmer/c/afc7a5834f0d [7/7] riscv: Add cache information in AUX vector https://git.kernel.org/palmer/c/da29dbcda49d Best regards, -- Palmer Dabbelt <palmer@xxxxxxxxxxxx>
