On 10/10/2022 05:41, Lad, Prabhakar wrote: > Hi Rob, Krzysztof, > > On Thu, Sep 29, 2022 at 6:24 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: >> >> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> >> >> Hi All, >> >> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts >> so that this can be shared with the RZ/Five SoC. >> >> Implementation is based on the discussion [0] where I have used option#2. >> >> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same >> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is >> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five >> (r9a07g043F.dtsi) >> >> Sending this as an RFC to get some feedback. >> >> r9a07g043f.dtsi will look something like below: >> >> #include <dt-bindings/interrupt-controller/irq.h> >> >> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32) >> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na >> >> #include <arm64/renesas/r9a07g043.dtsi> >> >> / { >> ... >> ... >> }; >> >> Although patch#2 can be merged into patch#1 just wanted to keep them separated >> for easier review. >> >> [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/ >> >> Cheers, >> Prabhakar >> >> Lad Prabhakar (2): >> arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro >> to specify interrupt property > > Can either of you please review patch #1. > Why? This is a DTS patch, isn't it? You should CC rather platform maintainers, architecture maintainers and SoC folks (the latter you missed for sure). You missed them, so please resend. Best regards, Krzysztof