On 10/10/2022 10:52, Biju Das wrote: > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer > channels and one 32-bit timer channel. It supports the following > functions > - Counter > - Timer > - PWM > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > v3->v4: > * Dropped counter and pwm compatibeles as they don't have any resources. > * Made rz-mtu3 as pwm provider. > * Updated the example and description. > v2->v3: > * Dropped counter bindings and integrated with mfd as it has only one property. > * Removed "#address-cells" and "#size-cells" as it do not have children with > unit addresses. > * Removed quotes from counter and pwm. > * Provided full path for pwm bindings. > * Updated the example. > v1->v2: > * Modelled counter and pwm as a single device that handles > multiple channels. > * Moved counter and pwm bindings to respective subsystems > * Dropped 'bindings' from MFD binding title. > * Updated the example > * Changed the compatible names. > --- > .../bindings/mfd/renesas,rz-mtu3.yaml | 305 ++++++++++++++++++ > 1 file changed, 305 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml This should not be in MFD. Just because some device has few features, does not mean it should go to MFD... Choose either timer or pwm. > > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml > new file mode 100644 > index 000000000000..1b0be9f5cd18 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/renesas,rz-mtu3.yaml > @@ -0,0 +1,305 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/renesas,rz-mtu3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a) > + > +maintainers: > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > + > +description: | > + This hardware block pconsisting of eight 16-bit timer channels and one "This hardware block consists of..." > + 32- bit timer channel. It supports the following specifications: > + - Pulse input/output: 28 lines max. > + - Pulse input 3 lines > + - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination > + (when LWA = 1)) > + - Operating frequency Up to 100 MHz Best regards, Krzysztof
