On Mon, 3 Oct 2022 10:26:44 +0100, Ben Dooks wrote: > On 29/09/2022 16:33, Conor Dooley wrote: > > On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote: > >> From: Emil Renner Berthing <kernel@xxxxxxxx> > >> > >> This cache controller is also used on the StarFive JH7100 and JH7110 > >> SoCs. > > > > Ditto this patch, hopefully [0] will have landed as 6.1 material > > before you get around to an actual v2. > > > > Thanks, > > Conor > > > > 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@xxxxxxxxxx/ > > Also, the l2 cache is being proprely named the ccache (composable cache) > as it is not necessarily an L2 cache. > Thanks for reminding. I will modify the code, based on the patches from Zong Li. I hope his patch series will be merged as soon as possible. Best regards, Hal
