On Fri, Oct 7, 2022 at 10:58 AM Palmer Dabbelt <palmer@xxxxxxxxxxx> wrote:
>
> On Sun, 28 Aug 2022 23:22:00 PDT (-0700), zong.li@xxxxxxxxxx wrote:
> > Since composible cache may be L3 cache if private L2 cache exists, it
> > should use its original name composible cache to prevent confusion.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@xxxxxxxxxx>
> > Signed-off-by: Zong Li <zong.li@xxxxxxxxxx>
> > ---
> > .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> > rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > similarity index 92%
> > rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > index 69cdab18d629..1a64a5384e36 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > @@ -12,8 +12,8 @@ maintainers:
> > - Paul Walmsley <paul.walmsley@xxxxxxxxxx>
> >
> > description:
> > - The SiFive Level 2 Cache Controller is used to provide access to fast copies
> > - of memory for masters in a Core Complex. The Level 2 Cache Controller also
> > + The SiFive Composable Cache Controller is used to provide access to fast copies
> > + of memory for masters in a Core Complex. The Composable Cache Controller also
> > acts as directory-based coherency manager.
> > All the properties in ePAPR/DeviceTree specification applies for this platform.
> >
> > @@ -27,6 +27,7 @@ select:
> > enum:
> > - sifive,fu540-c000-ccache
> > - sifive,fu740-c000-ccache
> > + - sifive,ccache0
>
> Looks like Rob's bot had comments and I don't see a v2. Sorry if I'm
> missing something.
Hi Palmer,
We moved this series to the following patch set:
http://lists.infradead.org/pipermail/linux-riscv/2022-October/020196.html
Sorry for the confusion. Many thanks for considering this series.
>
> Also: I'd guess that we only had the SOC-specific mappings on purpose.
> It's kind of a grey area and I'm OK either way, but I'd definately
> prefer the DT folks to get a chance to review these. My guess is that
> they're not looking due to the bot comments, but sorry again if I've
> missed it.
>
> > required:
> > - compatible
> > @@ -37,6 +38,7 @@ properties:
> > - enum:
> > - sifive,fu540-c000-ccache
> > - sifive,fu740-c000-ccache
> > + - sifive,ccache0
> > - const: cache
> >
> > cache-block-size:
