On 06.10.2022 10:44:48, Ivan Bornyakov wrote:
> Add support to the FPGA manager for programming Lattice ECP5 FPGA over
> slave SPI sysCONFIG interface.
>
> sysCONFIG interface core functionality is separate from both ECP5 and
> SPI specifics, so support for other FPGAs with different port types can
> be added in the future.
>
> Signed-off-by: Ivan Bornyakov <i.bornyakov@xxxxxxxxxxx>
> ---
[...]
> +static int sysconfig_spi_bitstream_burst_init(struct sysconfig_priv *priv)
> +{
> + const u8 lsc_bitstream_burst[] = SYSCONFIG_LSC_BITSTREAM_BURST;
I think you're not allowed to use stack memory for SPI transfers. Better
clarify this with the SPI people.
> + struct spi_device *spi = to_spi_device(priv->dev);
> + struct spi_transfer xfer = {
> + .tx_buf = lsc_bitstream_burst,
> + .len = sizeof(lsc_bitstream_burst),
> + .cs_change = 1,
> + };
> + struct spi_message msg;
> + int ret;
> +
> + spi_message_init_with_transfers(&msg, &xfer, 1);
> +
> + /*
> + * Lock SPI bus for exclusive usage until FPGA programming is done.
> + * SPI bus will be released in sysconfig_spi_bitstream_burst_complete().
> + */
> + spi_bus_lock(spi->controller);
> +
> + ret = spi_sync_locked(spi, &msg);
> + if (ret)
> + spi_bus_unlock(spi->controller);
> +
> + return ret;
> +}
regards,
Marc
--
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