From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> --- .../soc/renesas/r9a07g043f-l2-cache.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml new file mode 100644 index 000000000000..f96eeffa58ce --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive L2 Cache Controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a larger amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + + pma-regions: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 16 + description: Optional array of memory regions to be set as non-cacheable + bufferable regions which will be setup in the PMA. + +additionalProperties: false + +required: + - compatible + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + cache-controller@2010000 { + reg = <0x13400000 0x100000>; + compatible = "andestech,ax45mp-cache", "cache"; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + pma-regions = <0x00000000 0x10000000>, + <0x10000000 0x04000000>, + <0x20000000 0x10000000>, + <0x58000000 0x08000000>; + }; -- 2.25.1
