On Mon, 03 Oct 2022, Geert Uytterhoeven wrote: > Hi Lee, > > On Mon, Oct 3, 2022 at 9:34 AM Lee Jones <lee@xxxxxxxxxx> wrote: > > On Fri, 30 Sep 2022, Rob Herring wrote: > > > On Thu, Sep 29, 2022 at 06:53:49PM +0100, Lee Jones wrote: > > > > On Thu, 29 Sep 2022, Biju Das wrote: > > > > > > > > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in > > > > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer > > > > > channels and one 32-bit timer channel. It supports the following > > > > > functions > > > > > - Counter > > > > > - Timer > > > > > - PWM > > > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > > > > Not sure you need to list all of the IRQs in the example. > > > > > > You do, because that's what the schema says is valid. > > > > You have to use the exhaustive list? > > Yes, else "make dt_binding_check" fails to validate the example, > as the schema says all interrupts must be present. Okay, so all of those IRQs are compulsory? Makes sense then, thanks for the clarification. -- Lee Jones [李琼斯]
