Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
configuration.
Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 3610f94bef35..39b9a00d3ad8 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -235,6 +235,8 @@ uart7: serial@99c000 {
reg = <0x0 0x99c000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
+ reg = <0x0 0xf000000 0x0 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 151>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_default: qup-uart7-default {
+ tx {
+ pins = "gpio134";
+ function = "qup0_se7_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio135";
+ function = "qup0_se7_l3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.37.3
