Add additional QUP nodes and update previous nodes with
approrpiate interconnects and iommus.
Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 2fd449df3706..5d3932ad67a1 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -231,6 +231,15 @@ qupv3_id_0: geniqup@9c0000 {
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0xe3 0x0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0
+ &clk_virt SLAVE_QUP_CORE_0 0>;
+ interconnect-names = "qup-core";
+ qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+ qcom,iommu-geometry = <0x40000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ dma-coherent;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -250,6 +259,21 @@ uart7: serial@99c000 {
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0xac0000 0x0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x103 0x0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock-names = "m-ahb", "s-ahb";
+
+ ranges;
+ status = "disabled";
+ };
+
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss",
"qcom,cpufreq-epss";
--
2.37.3
