Add remaining UART instances to the QUP nodes for the QDU1000
and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 +++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 930bb8c8ba5b..21938e3a613e 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -290,6 +290,19 @@ qupv3_id_0: geniqup@9c0000 {
ranges;
status = "disabled";
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x980000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_default>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart7: serial@99c000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x99c000 0x0 0x4000>;
@@ -569,6 +582,33 @@ qupv3_id_1: geniqup@ac0000 {
ranges;
status = "disabled";
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0xa80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_default>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_default>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0xa84000 0x0 0x4000>;
@@ -912,7 +952,12 @@ tlmm: pinctrl@f000000 {
gpio-ranges = <&tlmm 0 0 151>;
wakeup-parent = <&pdc>;
- qup_uart7_default: qup-uart7-default {
+ qup_uart0_default: qup-uart0-default {
+ pins = "gpio6", "gpio7", "gpio8", "gpio9";
+ function = "qup0_se0_l0";
+ };
+
+ qup_uart7_default: qup-uart3-default {
tx {
pins = "gpio134";
function = "qup0_se7_l2";
@@ -928,6 +973,16 @@ rx {
};
};
+ qup_uart8_default: qup-uart8-default {
+ pins = "gpio18", "gpio19", "gpio20", "gpio21";
+ function = "qup1_se0_l0";
+ };
+
+ qup_uart13_default: qup-uart13-default {
+ pins = "gpio30", "gpio31", "gpio32", "gpio33";
+ function = "qup1_se5_l0";
+ };
+
qup_i2c1_data_clk: qup-i2c1-data-clk {
pins = "gpio10", "gpio11";
function = "qup0_se1_l0";
--
2.37.3
