On Tue, 27 Sep 2022 21:58:37 +0200, Gerhard Engleder wrote: > Within SoCs like ZynqMP, FPGA logic can be connected to different kinds > of AXI master ports. Also cache coherent AXI master ports are available. > The property "dma-coherent" is used to signal that DMA is cache > coherent. > > Add "dma-coherent" property to allow the configuration of cache coherent > DMA. > > Signed-off-by: Gerhard Engleder <gerhard@xxxxxxxxxxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
