On 26/09/2022 19:46, Gerhard Engleder wrote: >> That would be okay, but please add answer to why you are making this change. > > I already prepared it: > > Within SoCs like ZynqMP, FPGA logic can be connected to different kinds > of AXI master ports. Also cache coherent AXI master ports are available. > The property "dma-coherent" is used to signal that DMA is cache > coherent. > Add "dma-coherent" property to allow the configuration of cache coherent > DMA. > Sounds good, thanks. Best regards, Krzysztof
