Add Nodes to Radxa ROCK3 Model A board to support PCIe v3.
Also changed the vin-supply of vcc3v3_pcie regulator to
ensure that pcie is probe properly.
Signed-off-by: Chukun Pan <amadeus@xxxxxxxxxx>
---
.../boot/dts/rockchip/rk3568-rock-3a.dts | 52 ++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 1b195355da2a..097cee13885d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -67,6 +67,38 @@ vcc12v_dcin: vcc12v-dcin-regulator {
regulator-boot-on;
};
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* pi6c pcie clock generator */
+ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pi6c03";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* actually fed by vcc5v0_sys, dependent on pi6c clock generator */
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -76,7 +108,7 @@ vcc3v3_pcie: vcc3v3-pcie-regulator {
regulator-name = "vcc3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
+ vin-supply = <&vcc3v3_pi6c_03>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
@@ -547,6 +579,20 @@ &pcie2x1 {
status = "okay";
};
+&pcie30phy {
+ phy-supply = <&vcc3v3_pi6c_03>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ /* mPCIe slot */
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_reset_h>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
cam {
vcc_cam_en: vcc_cam_en {
@@ -583,6 +629,10 @@ pcie_enable_h: pcie-enable-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ minipcie_reset_h: minipcie-reset-h {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
ngffpcie_reset_h: ngffpcie-reset-h {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
--
2.25.1
