Enable MTU{1,2} for 16-bit phase count testing.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 2 --
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 11 ++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 25 ++++++++++++++++++-
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index bc2af6c92ccd..247b0b3f1b58 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -8,8 +8,6 @@
/dts-v1/;
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
-#include "rzg2l-smarc-pinfunction.dtsi"
-#include "rz-smarc-common.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 9085d8c76ce1..8c25c9f31ec0 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -53,17 +53,28 @@ i2c3_pins: i2c3 {
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
+#if (MTU3_PHASE_COUNTING_SUPPORT)
+ mtu3_pins: mtu3 {
+ mtu3_clk {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
+ <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTLCKB */
+ };
+ };
+#endif
+
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+#if (!MTU3_PHASE_COUNTING_SUPPORT)
scif2_pins: scif2 {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
};
+#endif
sd1-pwr-en-hog {
gpio-hog;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index e180a955b6ac..79b3088d2eda 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -9,7 +9,14 @@
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
-#define PMOD1_SER0 1
+#define PMOD1_SER0 0
+
+#if (!PMOD1_SER0)
+#define MTU3_PHASE_COUNTING_SUPPORT 1
+#endif
+
+#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rz-smarc-common.dtsi"
/ {
aliases {
@@ -36,6 +43,22 @@ wm8978: codec@1a {
};
};
+#if (MTU3_PHASE_COUNTING_SUPPORT)
+&mtu3 {
+ pinctrl-0 = <&mtu3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ counter@1 {
+ status = "okay";
+ };
+
+ counter@2 {
+ status = "okay";
+ };
+};
+#endif
+
/*
* To enable SCIF2 (SER0) on PMOD1 (CN7)
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
--
2.25.1
