On 9/21/22 2:57 AM, Krzysztof Kozlowski wrote: > On Tue, 20 Sep 2022 16:23:50 -0400, Sean Anderson wrote: >> This adds a binding for the SerDes module found on QorIQ processors. >> Each phy is a subnode of the top-level device, possibly supporting >> multiple lanes and protocols. This "thick" #phy-cells is used due to >> allow for better organization of parameters. Note that the particular >> parameters necessary to select a protocol-controller/lane combination >> vary across different SoCs, and even within different SerDes on the same >> SoC. >> >> The driver is designed to be able to completely reconfigure lanes at >> runtime. Generally, the phy consumer can select the appropriate >> protocol using set_mode. >> >> There are two PLLs, each of which can be used as the master clock for >> each lane. Each PLL has its own reference. For the moment they are >> required, because it simplifies the driver implementation. Absent >> reference clocks can be modeled by a fixed-clock with a rate of 0. >> >> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx> >> Reviewed-by: Rob Herring <robh@xxxxxxxxxx> >> --- >> >> Changes in v6: >> - fsl,type -> phy-type >> >> Changes in v4: >> - Use subnodes to describe lane configuration, instead of describing >> PCCRs. This is the same style used by phy-cadence-sierra et al. >> >> Changes in v3: >> - Manually expand yaml references >> - Add mode configuration to device tree >> >> Changes in v2: >> - Rename to fsl,lynx-10g.yaml >> - Refer to the device in the documentation, rather than the binding >> - Move compatible first >> - Document phy cells in the description >> - Allow a value of 1 for phy-cells. This allows for compatibility with >> the similar (but according to Ioana Ciornei different enough) lynx-28g >> binding. >> - Remove minItems >> - Use list for clock-names >> - Fix example binding having too many cells in regs >> - Add #clock-cells. This will allow using assigned-clocks* to configure >> the PLLs. >> - Document the structure of the compatible strings >> >> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 236 ++++++++++++++++++ >> 1 file changed, 236 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Error: Documentation/devicetree/bindings/phy/fsl,lynx-10g.example.dts:51.27-28 syntax error > FATAL ERROR: Unable to parse input tree > make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/phy/fsl,lynx-10g.example.dtb] Error 1 > make[1]: *** Waiting for unfinished jobs.... > make: *** [Makefile:1420: dt_binding_check] Error 2 > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/ > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. > I believe this is due to the previous patch not being applied, same as last time. --Sean
