Hi Matthias,
Thanks for the review.
On Thu, 2022-09-15 at 18:15 +0200, Matthias Brugger wrote:
>
> On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> > pipelines binding to 1 mmsys with the same power domain, the same
> > clock driver and the same mediatek-drm driver.
> >
> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
> > to
> > 2 different power domains, different clock drivers and different
> > mediatek-drm drivers.
> >
> > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
> > Quality)
> > and they makes VDOSYS0 supports PQ function while they are not
> > including in VDOSYS1.
> >
> > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> > component). It makes VDOSYS1 supports the HDR function while it's
> > not
> > including in VDOSYS0.
> >
> > To summarize0:
> > Only VDOSYS0 can support PQ adjustment.
> > Only VDOSYS1 can support HDR adjustment.
> >
> > Therefore, we need to separate these two different mmsys hardwares
> > to
> > 2 different compatibles for MT8195.
> >
> > Fixes: b852ee68fd72 ("arm64: dts: mt8195: Add display node for
> > vdosys0")
>
> No fixes tag needed, there is no runtime bug.
>
> Regards,
> Matthias
>
OK, I'll remove this.
But I think this dts change should be sent after the vdosys1 series are
accepted.
So I'll drop this dts patch at the next version.
Regards,
Jason-JH.Lin
> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@xxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 905d1a90b406..6ec6d59a16ec 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1966,7 +1966,7 @@
> > };
> >
> > vdosys0: syscon@1c01a000 {
> > - compatible = "mediatek,mt8195-mmsys", "syscon";
> > + compatible = "mediatek,mt8195-vdosys0",
> > "syscon";
> > reg = <0 0x1c01a000 0 0x1000>;
> > mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
> > #clock-cells = <1>;
> > @@ -2101,7 +2101,7 @@
> > };
> >
> > vdosys1: syscon@1c100000 {
> > - compatible = "mediatek,mt8195-mmsys", "syscon";
> > + compatible = "mediatek,mt8195-vdosys1",
> > "syscon";
> > reg = <0 0x1c100000 0 0x1000>;
> > #clock-cells = <1>;
> > };
>
>
--
Jason-JH Lin <jason-jh.lin@xxxxxxxxxxxx>
