On 13/09/2022 11:33, Sascha Hauer wrote:
> Add the InnoComm i.MX8MM based WB15 SoM and its EVK. The WB15 is a
> half credit card sized board featuring:
>
> - i.MX8MM CPU
> - LPDDR4, 1GiB
> - eMMC, 8GiB
> - 1Gb Ethernet RGMII interface
> - WiFi 802.11 a/b/g/n/ac, Bluetooth 4.2
>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Thank you for your patch. There is something to discuss/improve.
> + pinctrl_fec: fecgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
> + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
> + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + >;
> + };
> +
> + pinctrl_fec_phy: fecphygrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + >;
> + };
> +
> + pinctrl_fec_phy_reg: fecphyreggrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
> + >;
> + };
> +
> + pinctrl_gpio_leds: led_grp {
No underscores in node names.
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
> + >;
> + };
> +
> + pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + >;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> new file mode 100644
> index 0000000000000..4a20508d560dd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> @@ -0,0 +1,480 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2018 Bang & Olufsen
> + */
> +
> +#include "imx8mm.dtsi"
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> +/ {
> + reg_modem: regulator-modem {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_modem_regulator>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "epdev_on";
> + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +
> + reg_3v3_out: regulator-3v3-out {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3_OUT";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +};
> +
> +&cpu_alert0 {
> + temperature = <95000>;
> +};
> +
> +&cpu_crit0 {
> + temperature = <105000>;
> +};
> +
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25000000 {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> +
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
> + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + pmic@4b {
> + compatible = "rohm,bd71847";
> + reg = <0x4b>;
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;
Wrong flag. This is very old bug. Please base your work on recent DTSes.
Don't start with vendor/downstream DTS because it contains bugs. Instead
take recent mainline and customize it for the manufacturer.
> + rohm,reset-snvs-powered;
> +
Best regards,
Krzysztof
