Add second clock phandle to specify the timestamping clock.
Signed-off-by: Matej Vasilevski <matej.vasilevski@xxxxxxxxx>
---
.../bindings/net/can/ctu,ctucanfd.yaml | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
index 4635cb96fc64..432f0e3ed828 100644
--- a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
+++ b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
@@ -44,9 +44,19 @@ properties:
clocks:
description: |
- phandle of reference clock (100 MHz is appropriate
- for FPGA implementation on Zynq-7000 system).
- maxItems: 1
+ Phandle of reference clock (100 MHz is appropriate for FPGA
+ implementation on Zynq-7000 system). Optionally add a phandle to
+ the timestamping clock connected to timestamping counter, if used.
+ minItems: 1
+ items:
+ - description: core clock
+ - description: timestamping clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core-clk
+ - const: ts-clk
required:
- compatible
@@ -61,6 +71,7 @@ examples:
ctu_can_fd_0: can@43c30000 {
compatible = "ctu,ctucanfd";
interrupts = <0 30 4>;
- clocks = <&clkc 15>;
+ clocks = <&clkc 15>, <&clkc 16>;
+ clock-names = "core-clk", "ts-clk";
reg = <0x43c30000 0x10000>;
};
--
2.25.1
