There is mmio based mdio mux function in the FPGA device on ls1043a-qds
board. Add the mmio based mdio-mux nodes to ls1043a-qds boards and
add simple-mfd as a compatbile for the FPGA node to reflect the
multi-function nature of it. Also connect the ethernet interfaces to
these phy interfaces.
Signed-off-by: Li Yang <leoyang.li@xxxxxxx>
---
.../boot/dts/freescale/fsl-ls1043a-qds.dts | 173 +++++++++++++++++-
1 file changed, 171 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index fea167d222cf..9b726c2a4842 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
*
* Mingkai Hu <Mingkai.hu@xxxxxxxxxxxxx>
*/
@@ -24,6 +24,22 @@ aliases {
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+ sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
+ sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
+ sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
+ qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
+ qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
+ qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
+ qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
+ emi1-slot1 = &ls1043mdio_s1;
+ emi1-slot2 = &ls1043mdio_s2;
+ emi1-slot3 = &ls1043mdio_s3;
+ emi1-slot4 = &ls1043mdio_s4;
};
chosen {
@@ -62,8 +78,11 @@ nand@1,0 {
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <0x2 0x0 0x0000100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 2 0 0x100>;
};
};
@@ -153,3 +172,153 @@ &usb0 {
};
#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&qsgmii_phy_s2_p2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&qsgmii_phy_s2_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&qsgmii_phy_s2_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ fixed-link = <1 1 10000 0 0>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ mdio-mux-emi1@54 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1043mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1043mdio1: mdio@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1043mdio_s1: mdio@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s1_p1: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ qsgmii_phy_s1_p2: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ qsgmii_phy_s1_p3: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ qsgmii_phy_s1_p4: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1043mdio_s2: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+
+ sgmii_phy_s2_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 3 */
+ ls1043mdio_s3: mdio@80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s3_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1043mdio_s4: mdio@a0 {
+ reg = <0xa0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--
2.37.1
