On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote: > Update bindings for TI K3 J721e SoC which contains 9 ports (8 external > ports) CPSW9G module and add compatible for it. > > Changes made: > - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. > - Extend pattern properties for new compatible. > - Change maximum number of CPSW ports to 8 for new compatible. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> > --- > .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) What's the base for this patch? It didn't apply for me. Run 'make dt_binding_check'. It should point out the issue I did. If not, let me know. Rob
