Hi Chris, On 9/12/22 22:56, Chris Morgan wrote: > From: Chris Morgan <macromorgan@xxxxxxxxxxx> > > This series adds support for the dsi and dphy controllers on the > Rockchip RK3568. > > Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance. > > Changes since V2: > - Removed dsi controller patches, as those have been merged upstream. > - Removed notes about rolling back clock drivers. If I set the parent > clock of the VOP port I'm using to VPLL and set the clock rate of > PLL_VPLL to 500MHz this series works correctly for my panels without > rolling anything back (per Heiko this is the correct way). I tried this but it didn't help (neither did reverting ff3187eabb5c "clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568"). On my display the content is shifted horizontally and the colors are often wrong. > - Added additional details about refactoring DPHY driver to add > 2.5GHz for rk356x. All other devices still have a max speed of 1GHz. > - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and > PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the > phy_update_bits() works. > > Changes since RFCv1: > - Identified cause of image shift (clock changes). > - Noted that driver works now. > - Added devicetree nodes for rk356x.dtsi. > > Chris Morgan (3): > dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568 > phy/rockchip: inno-dsidphy: Add support for rk3568 > arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x I am testing this on a RK3568 EVB1, which has a display mounted on the PCB. I'll submit the patches that add support for this setup soon. For the time being a preliminary Tested-by: Michael Riesch <michael.riesch@xxxxxxxxxxxxxx> Thanks for your work! Best regards, Michael > > .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 72 +++++++ > .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++++++++++++++---- > 3 files changed, 231 insertions(+), 46 deletions(-) >
