On Sat, Sep 10, 2022 at 05:32:11PM +0300, Iskren Chernev wrote:
[..]
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
[..]
> +
> + smem {
> + compatible = "qcom,smem";
Please move the compatible, qcom,rpm-msg-ram and hwlocks into the
&smem_mem node.
> + memory-region = <&smem_mem>;
> + qcom,rpm-msg-ram = <&rpm_msg_ram>;
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> + soc: soc {
I expect that you should be told that you're missing a @0 on your soc.
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + tlmm: pinctrl@500000 {
Please sort your nodes based on address, followed by node name
alphabetically, followed by label.
> + compatible = "qcom,sm6115-tlmm";
> + reg = <0x500000 0x400000>, <0x900000 0x400000>, <0xd00000 0x400000>;
Please pad your address to 8 digits, to make it faster to see if the
sort order makes sense.
> + reg-names = "west", "south", "east";
> + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + gpio-ranges = <&tlmm 0 0 121>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
[..]
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 0xf08>,
> + <GIC_PPI 2 0xf08>,
> + <GIC_PPI 3 0xf08>,
> + <GIC_PPI 0 0xf08>;
Please use (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) for your flags.
Regards,
Bjorn
