Hi Horatiu, Am 2022-09-12 21:26, schrieb Horatiu Vultur:
According to the datasheet the interrupts for internal PHYs are 80 and 81.
Can you point me to that documentation? Accoring to Table 3-155: Shared Peripheral Interrupts There are ID47 and ID48 listed as "MIIM controller 0 interrupt". Whatever that is, because the internal PHYs are on MIIM controller 1. But 80 and 81 would be ID48 and ID49. Did you test the interrupts? -michael
Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes") Signed-off-by: Horatiu Vultur <horatiu.vultur@xxxxxxxxxxxxx> --- arch/arm/boot/dts/lan966x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsiindex bcb130a2471d..23665a042990 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -547,13 +547,13 @@ mdio1: mdio@e200413c { phy0: ethernet-phy@1 { reg = <1>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; phy1: ethernet-phy@2 { reg = <2>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; };
