On Sat, 10 Sep 2022 22:56:48 +0300, Serge Semin wrote: > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > are individual IRQs for each ECC and DFI events. The dedicated scrubber > clock source is absent since it's fully synchronous to the core clock. > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > registers space. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > > --- > > Changelog v2: > - Keep the alphabetically ordered compatible strings list. (@Krzysztof) > - Fix grammar nitpicks in the patch log. (@Krzysztof) > - Drop the PHY CSR region. (@Rob) > - Move the device bindings to the separate DT-schema. > --- > .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
