On Sat, Sep 10, 2022 at 10:56:46PM +0300, Serge Semin wrote: > First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines > for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC > Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's > possible that the platform engineers merge them up in the IRQ controller > level. So let's add both configuration support to the DT-schema. > > Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB > reference clock, AXI-ports clock, main DDRC core reference clock and > Scrubber low-power clock. In addition to that each clock domain can have a > dedicated reset signal. Let's add the properties for at least the denoted > clock sources and the corresponding reset controls. > > Note the IRQs and the phandles order is deliberately not fixed since some > of the sources may be absent depending on the IP-core synthesize > parameters and the particular platform setups. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > > --- > > Changelog v2: > - Replace "snps,ddrc-3.80a" compatible string with "snps,dw-umctl2-ddrc" > in the example. > - Move unrelated changes in to the dedicated patches. (@Krzysztof) > - Use the IRQ macros in the example. (@Krzysztof) > --- > .../snps,dw-umctl2-ddrc.yaml | 61 ++++++++++++++++++- > 1 file changed, 60 insertions(+), 1 deletion(-) Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
