Tegra234 has eight single-channel PWM controllers, one of them in the
AON block.
Signed-off-by: Sandipan Patra <spatra@xxxxxxxxxx>
---
V3: Update binding doc and fix compatible property.
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 80 +++++++++++++++++++++++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 81a0f599685f..d77ee9d81fb2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -829,8 +829,7 @@
};
pwm1: pwm@3280000 {
- compatible = "nvidia,tegra194-pwm",
- "nvidia,tegra186-pwm";
+ compatible = "nvidia,tegra194-pwm";
reg = <0x3280000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM1>;
clock-names = "pwm";
@@ -840,6 +839,83 @@
#pwm-cells = <2>;
};
+ pwm2: pwm@3290000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0x3290000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM2>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM2>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@32a0000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0x32a0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM3>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM3>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm4: pwm@c340000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0xc340000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM4>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM4>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm5: pwm@32c0000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0x32c0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM5>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM5>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm6: pwm@32d0000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0x32d0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM6>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM6>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm7: pwm@32e0000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0x32e0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM7>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM7>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm8: pwm@32f0000 {
+ compatible = "nvidia,tegra194-pwm";
+ reg = <0x32f0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM8>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM8>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
spi@3300000 {
compatible = "nvidia,tegra234-qspi";
reg = <0x3300000 0x1000>;
--
2.17.1
