On 09/09/2022 17:24, Maxime Chevallier wrote:
> The Qualcomm IPQESS controller is a simple 1G Ethernet controller found
> on the IPQ4019 chip. This controller has some specificities, in that the
> IPQ4019 platform that includes that controller also has an internal
> switch, based on the QCA8K IP.
>
> It is connected to that switch through an internal link, and doesn't
> expose directly any external interface, hence it only supports the
> PHY_INTERFACE_MODE_INTERNAL for now.
>
> It has 16 RX and TX queues, with a very basic RSS fanout configured at
Thank you for your patch. There is something to discuss/improve.
> +}
> +
> +static int ipqess_axi_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct net_device *netdev;
> + phy_interface_t phy_mode;
> + struct resource *res;
> + struct ipqess *ess;
> + int i, err = 0;
> +
> + netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct ipqess),
sizeof(*)
> + IPQESS_NETDEV_QUEUES,
> + IPQESS_NETDEV_QUEUES);
> + if (!netdev)
> + return -ENOMEM;
> +
> + ess = netdev_priv(netdev);
> + ess->netdev = netdev;
> + ess->pdev = pdev;
> + spin_lock_init(&ess->stats_lock);
> + SET_NETDEV_DEV(netdev, &pdev->dev);
> + platform_set_drvdata(pdev, netdev);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + ess->hw_addr = devm_ioremap_resource(&pdev->dev, res);
Use a helper for this.
> + if (IS_ERR(ess->hw_addr))
> + return PTR_ERR(ess->hw_addr);
> +
> + err = of_get_phy_mode(np, &phy_mode);
> + if (err) {
> + dev_err(&pdev->dev, "incorrect phy-mode\n");
> + return err;
> + }
> +
> + ess->ess_clk = devm_clk_get(&pdev->dev, "ess");
There is no such clock "ess"...
> + if (!IS_ERR(ess->ess_clk))
> + clk_prepare_enable(ess->ess_clk);
> +
> + ess->ess_rst = devm_reset_control_get(&pdev->dev, "ess");
Same problem.
> + if (IS_ERR(ess->ess_rst))
> + goto err_clk;
> +
> + ipqess_reset(ess);
> +
> + ess->phylink_config.dev = &netdev->dev;
> + ess->phylink_config.type = PHYLINK_NETDEV;
> + ess->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
> + MAC_100 | MAC_1000FD;
> +
> + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
> + ess->phylink_config.supported_interfaces);
> +
> + ess->phylink = phylink_create(&ess->phylink_config,
> + of_fwnode_handle(np), phy_mode,
> + &ipqess_phylink_mac_ops);
> + if (IS_ERR(ess->phylink)) {
> + err = PTR_ERR(ess->phylink);
> + goto err_clk;
> + }
> +
Best regards,
Krzysztof
