Hey Shravan, Please don't drop the lists etc from CC. On 08/09/2022 12:29, shravan Chippa - I35088 wrote:> >> -----Original Message----- >> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> >> Sent: 08 September 2022 04:47 PM >> To: Rob Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski >> <krzysztof.kozlowski+dt@xxxxxxxxxx>; Conor Dooley - M52691 >> <Conor.Dooley@xxxxxxxxxxxxx>; Daire McNamara - X61553 >> <Daire.McNamara@xxxxxxxxxxxxx>; shravan Chippa - I35088 >> <Shravan.Chippa@xxxxxxxxxxxxx> >> Cc: Paul Walmsley <paul.walmsley@xxxxxxxxxx>; Palmer Dabbelt >> <palmer@xxxxxxxxxxx>; Albert Ou <aou@xxxxxxxxxxxxxxxxx>; Cyril Jean - >> M31571 <Cyril.Jean@xxxxxxxxxxxxx>; Lewis Hanly - M34782 >> <Lewis.Hanly@xxxxxxxxxxxxx>; Praveen Kumar - I30718 >> <Praveen.Kumar@xxxxxxxxxxxxx>; Wolfgang Grandegger <wg@aries- >> embedded.de>; Hugh Breslin - M31864 <Hugh.Breslin@xxxxxxxxxxxxx>; >> devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux- >> kernel@xxxxxxxxxxxxxxx >> Subject: [PATCH v4 10/10] riscv: dts: microchip: add a devicetree for aries' >> m100pfsevp >> >> Add device trees for both configs used by the Aries Embedded M100PFSEVP. >> The M100OFSEVP consists of a MPFS250T on a SOM, >> featuring: >> - 2GB DDR4 SDRAM dedicated to the HMS >> - 512MB DDR4 SDRAM dedicated to the FPGA >> - 32 MB SPI NOR Flash >> - 4 GByte eMMC >> >> and a carrier board with: >> - 2x Gigabit Ethernet >> - USB >> - 2x UART >> - 2x CAN >> - TFT connector >> - HSMC extension connector >> - 3x PMOD extension connectors >> - microSD-card slot >> >> Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi- >> m100pfs-som-mpfs025t-pcie-serdes >> Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire- >> microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod >> Link: https://downloads.aries- >> embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf >> Co-developed-by: Wolfgang Grandegger <wg@xxxxxxxxxxxxxxxxx> >> Signed-off-by: Wolfgang Grandegger <wg@xxxxxxxxxxxxxxxxx> >> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> >> diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts >> b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts >> new file mode 100644 >> index 000000000000..184cb36a175e >> --- /dev/null >> +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts >> @@ -0,0 +1,179 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Original all-in-one devicetree: >> + * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries- >> embedded.de> >> + * Rewritten to use includes: >> + * Copyright (C) 2022 - Conor Dooley <conor.dooley@xxxxxxxxxxxxx> */ >> +/dts-v1/; >> + >> +#include "mpfs.dtsi" >> +#include "mpfs-m100pfs-fabric.dtsi" >> + >> +/* Clock frequency (in Hz) of the rtcclk */ >> +#define MTIMER_FREQ 1000000 >> + >> +/ { >> + model = "Aries Embedded M100PFEVPS"; >> + compatible = "aries,m100pfsevp", "microchip,mpfs"; >> + >> + aliases { >> + ethernet0 = &mac0; >> + ethernet1 = &mac1; >> + serial0 = &mmuart0; >> + serial1 = &mmuart1; >> + serial2 = &mmuart2; >> + serial3 = &mmuart3; >> + serial4 = &mmuart4; >> + gpio0 = &gpio0; >> + gpio1 = &gpio2; >> + }; >> + >> + chosen { >> + stdout-path = "serial1:115200n8"; >> + }; >> + >> + cpus { >> + timebase-frequency = <MTIMER_FREQ>; >> + }; >> + >> + ddrc_cache_lo: memory@80000000 { >> + device_type = "memory"; >> + reg = <0x0 0x80000000 0x0 0x40000000>; >> + }; >> + ddrc_cache_hi: memory@1040000000 { >> + device_type = "memory"; >> + reg = <0x10 0x40000000 0x0 0x40000000>; >> + }; >> +}; >> + >> +&can0 { >> + status = "okay"; >> +}; >> + >> +&i2c0 { >> + status = "okay"; >> +}; >> + >> +&i2c1 { >> + status = "okay"; >> +}; >> + >> +&gpio0 { >> + interrupts = <13>, <14>, <15>, <16>, >> + <17>, <18>, <19>, <20>, >> + <21>, <22>, <23>, <24>, >> + <25>, <26>; > > Commented bellow... > >> + ngpios = <14>; >> + status = "okay"; >> + >> + pmic-irq-hog { >> + gpio-hog; >> + gpios = <13 0>; >> + input; >> + }; >> + >> + /* Set to low for eMMC, high for SD-card */ >> + mmc-sel-hog { >> + gpio-hog; >> + gpios = <12 0>; >> + output-high; >> + }; >> +}; >> + >> +&gpio2 { >> + interrupts = <13>, <14>, <15>, <16>, >> + <17>, <18>, <19>, <20>, >> + <21>, <22>, <23>, <24>, >> + <25>, <26>, <27>, <28>, >> + <29>, <30>, <31>, <32>, >> + <33>, <34>, <35>, <36>, >> + <37>, <38>, <39>, <40>, >> + <41>, <42>, <43>, <44>; >> + status = "okay"; >> +}; > > Same interrupt numbers GPIO2 and GPIO0? > > As per my understanding, GPIO2 and GPIO0 are using maxed interrupt lines > Only one bank GPIO0/GPIO2 can work in direct interrupt mode > other should be in non-direct interrupt mode. Yeah, good spot - this cannot be correct. I had a look in the HSS and there does not appear to be anything setting the GPIO_INTERRUPT_FAB_CR for the m100pfsevp target & therefore would be at its default value of 0 - so GPIO2 should be using interrupt 53 for all GPIOs. Thanks, Conor. >> + >> +&mac0 { >> + status = "okay"; >> + phy-mode = "gmii"; >> + phy-handle = <&phy0>; >> + phy0: ethernet-phy@0 { >> + reg = <0>; >> + }; >> +}; >> + >> +&mac1 { >> + status = "okay"; >> + phy-mode = "gmii"; >> + phy-handle = <&phy1>; >> + phy1: ethernet-phy@0 { >> + reg = <0>; >> + }; >> +}; >> + >> +&mbox { >> + status = "okay"; >> +}; >> + >> +&mmc { >> + max-frequency = <50000000>; >> + bus-width = <4>; >> + cap-mmc-highspeed; >> + cap-sd-highspeed; >> + no-1-8-v; >> + sd-uhs-sdr12; >> + sd-uhs-sdr25; >> + sd-uhs-sdr50; >> + sd-uhs-sdr104; >> + disable-wp; >> + status = "okay"; >> +}; >> + >> +&mmuart1 { >> + status = "okay"; >> +}; >> + >> +&mmuart2 { >> + status = "okay"; >> +}; >> + >> +&mmuart3 { >> + status = "okay"; >> +}; >> + >> +&mmuart4 { >> + status = "okay"; >> +}; >> + >> +&pcie { >> + status = "okay"; >> +}; >> + >> +&qspi { >> + status = "okay"; >> +}; >> + >> +&refclk { >> + clock-frequency = <125000000>; >> +}; >> + >> +&rtc { >> + status = "okay"; >> +}; >> + >> +&spi0 { >> + status = "okay"; >> +}; >> + >> +&spi1 { >> + status = "okay"; >> +}; >> + >> +&syscontroller { >> + status = "okay"; >> +}; >> + >> +&usb { >> + status = "okay"; >> + dr_mode = "host"; >> +}; >> -- >> 2.36.1 >
