On 06/09/2022 11:00, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@xxxxxxx> > > i.MX8M Family features an anatop module the produces PLL to clock > control module(CCM) root clock. Add the missing yaml file. > > Signed-off-by: Peng Fan <peng.fan@xxxxxxx> > --- > .../bindings/clock/imx8m-anatop.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/imx8m-anatop.yaml > > diff --git a/Documentation/devicetree/bindings/clock/imx8m-anatop.yaml b/Documentation/devicetree/bindings/clock/imx8m-anatop.yaml > new file mode 100644 > index 000000000000..e247a5774d17 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/imx8m-anatop.yaml Filename: fsl,imx8m-anatop.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/imx8m-anatop.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX8M Family Anatop Module > + > +maintainers: > + - Peng Fan <peng.fan@xxxxxxx> > + > +description: | > + NXP i.MX8M Family anatop PLL module which generates PLL to CCM root. Description suggests it is a clock controller (you literally write it generates PLL), but bindings are for system registers (syscon). If it is PLL, you should make it a real clock provider. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - fsl,imx8mm-anatop > + - fsl,imx8mq-anatop > + - const: syscon > + - items: > + - enum: > + - fsl,imx8mn-anatop > + - fsl,imx8mp-anatop > + - const: fsl,imx8mm-anatop > + - const: syscon > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + anatop: anatop@30360000 { Node name: syscon or clock-controller if it is a clock provider. > + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", "syscon"; > + reg = <0x30360000 0x10000>; > + }; > + > +... Best regards, Krzysztof
