On Thu, Sep 01, 2022 at 01:23:12PM +0300, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8250 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- > .../bindings/display/msm/dpu-sm8250.yaml | 96 ++++++++++++++++ > .../bindings/display/msm/mdss-common.yaml | 4 +- > .../bindings/display/msm/mdss-sm8250.yaml | 106 ++++++++++++++++++ > 3 files changed, 204 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml > new file mode 100644 > index 000000000000..9bc2ee4a6589 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dpu-sm8250.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display DPU dt properties for SM8250 Qualcomm SM8250 Display DPU > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > + > +description: | > + Device tree bindings for the DPU display controller for SM8250 target. If you don't have more to say than the title, then just drop. > + > +allOf: > + - $ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8250-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display ahb clock > + - description: Display hf axi clock > + - description: Display core clock > + - description: Display vsync clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + - const: vsync > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> > + #include <dt-bindings/clock/qcom,gcc-sm8250.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,sm8250.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@ae01000 { > + compatible = "qcom,sm8250-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "core", "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8250_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml > index 053c1e889552..a0a54cd63100 100644 > --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml > +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml > @@ -27,11 +27,11 @@ properties: > > clocks: > minItems: 2 > - maxItems: 3 > + maxItems: 4 > > clock-names: > minItems: 2 > - maxItems: 3 > + maxItems: 4 > > interrupts: > maxItems: 1 > diff --git a/Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml b/Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml > new file mode 100644 > index 000000000000..d581d10fea2d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml > @@ -0,0 +1,106 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/mdss-sm8250.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display MDSS dt properties for SM8250 target Same comment here. > + > +maintainers: > + - Krishna Manikandan <quic_mkrishn@xxxxxxxxxxx> > + > +description: | > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree > + bindings of MDSS are mentioned for SM8250 target. > + > +allOf: > + - $ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm8250-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display hf axi clock > + - description: Display sf axi clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm8250-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,mdss-dsi-ctrl > + > + "^dsi-phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-7nm > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> > + #include <dt-bindings/clock/qcom,gcc-sm8250.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,sm8250.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-subsystem@ae00000 { > + compatible = "qcom,sm8250-mdss"; > + reg = <0x0ae00000 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, > + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; Drop > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + }; > +... > -- > 2.35.1 > >
