On 14-10-10 03:08 AM, Arnd Bergmann wrote:
On Thursday 09 October 2014 15:44:29 Scott Branden wrote:
+
+ lcpll: lcpll@0301d02c {
+ #clock-cells = <0>;
+ compatible = "brcm,cygnus-lcpll-clk";
+ reg = <0x0301d02c 0x1c>;
+ clocks = <&osc>;
+ };
+
+ genpll: genpll@0301d000 {
+ #clock-cells = <0>;
+ compatible = "brcm,cygnus-genpll-clk";
+ reg = <0x0301d000 0x2c>,
+ <0x180AA024 0x4>,
+ <0x0301C020 0x4>;
+ clocks = <&osc>;
+ };
+
To be honest, I'm not too happy about the way you specify a single
register for each clock as a global 'reg' property.
I'm not happy with this either. Will rework.
Presumably each of these registers is part of an IP block that does
multiple things, so it would be better to start out with a binding
for each IP block. How many of these blocks are used for clocks, and
what do they do?
Clocks are a little scattered in the chip and don't make a lot of sense
for easy software programming. Will look at how to change bindings so
they are flexible to work on other generations.
Arnd
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