The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most
of the new clocks, GDSCs, and resets already have reserved IDs but there
are some resources that don't. Add the new clock and extra BCR from
Snapdragon 670 and document the differences between the SoC parent clocks.
Signed-off-by: Richard Acayan <mailingradian@xxxxxxxxx>
---
.../bindings/clock/qcom,gcc-sdm845.yaml | 24 +++++++++++++++----
include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/defaced/bindings/clock/qcom,gcc-sdm845.yaml
index daf7906ebc40..ba94dd32e619 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
@@ -19,23 +19,21 @@ description: |
properties:
compatible:
- const: qcom,gcc-sdm845
+ enum:
+ - qcom,gcc-sdm670
+ - qcom,gcc-sdm845
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- - description: PCIE 0 Pipe clock source
- - description: PCIE 1 Pipe clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- - const: pcie_0_pipe_clk
- - const: pcie_1_pipe_clk
'#clock-cells':
const: 1
@@ -63,6 +61,22 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,gcc-sdm845
+then:
+ properties:
+ clocks:
+ items:
+ - description: PCIE 0 Pipe clock source
+ - description: PCIE 1 Pipe clock source
+ clock-names:
+ items:
+ - const: pcie_0_pipe_clk
+ - const: pcie_1_pipe_clk
+
additionalProperties: false
examples:
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
index 968fa65b9c42..9fef78fd031d 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -199,6 +199,7 @@
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
#define GCC_LPASS_Q6_AXI_CLK 190
#define GCC_LPASS_SWAY_CLK 191
+#define GPLL6 192
/* GCC Resets */
#define GCC_MMSS_BCR 0
@@ -227,6 +228,7 @@
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
#define GCC_PCIE_0_PHY_BCR 24
#define GCC_PCIE_1_PHY_BCR 25
+#define GCC_SDCC1_BCR 26
/* GCC GDSCRs */
#define PCIE_0_GDSC 0
--
2.37.3
