From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> Hi all, This series includes an attempt to deal with the PCIe address translation behaviour of Microchip PolarFire SoC. On this chip, FPGA logic exists between the PCIe rootport and the CPUs (Core Complex). So, outbound and inbound translation to PCIe devices is achieved by a combination of individual customer's FPGA fabric designs and by the PCIe rootport itself and thus the outbound and inbound address translation specified in range properties and dma-range properties of the PCIe rootport appears insufficient as they do not capture how much outbound and inbound address translation has occured in the FPGA design between the addresses used by the CPU and the addresses used by the PCIe devices. So, we require some mechanism to inform the root port of what address translation it actually needs to perform in order to achieve the goals specified in the range and dma-range properties. This series proposes two new Microchip properties, each in the form of ranges, which capture the amount of outbound and inbound translation done by the FPGA fabric, if any. If the new properties are absent, the range and dma-range properties are intended to be parsed by the root port driver as usual, and the entire specified address translation is carried out by the root port using its address translation tables. if one of the new properties are present, the translations carried out by the rootport, as specified in the range or dma-range properties, are adjusted by the amount of address translation carried out by the FPGA design, as described in the details of the new properties. The new properties are structured as ranges to enable FPGA designers to have different address translation ranges; for example, an FPGA designer may choose to partition 32-bit address translation and 38-bit translation through different apertures for their particular design or may choose to target non-cached and/or cached DDR with different dma-ranges. This series contains a proposed new binding for the properties, and an implementation of the new properties for the Microchip PolarFire SoC PCIe rootport driver. Thanks, Daire Conor Dooley (1): dt-bindings: PCI: microchip: add fabric address translation properties Daire McNamara (3): riscv: dts: microchip: add fabric address translation properties PCI: microchip: add fabric address translation properties of: PCI: tidy up logging of ranges containing configuration space type .../bindings/pci/microchip,pcie-host.yaml | 107 ++++++++++++++++++ .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 6 +- drivers/pci/controller/pcie-microchip-host.c | 59 ++++++++-- drivers/pci/of.c | 2 + 4 files changed, 166 insertions(+), 8 deletions(-) base-commit: 6496a28df951641c0d50052ee195c7765591ff92 prerequisite-patch-id: 39bd182e929a064e38ca191a1726dd6d5a620f2d prerequisite-patch-id: 9401b90950832090dabfe5f74f525ed4fa1c1410 prerequisite-patch-id: 606a8ca57d3dc19b04490b6e75d267a7c0d76163 -- 2.25.1
