On 01/09/2022 10:24, Iskren Chernev wrote:
> The SM6115 comes with UFS support, so add the related UFS and UFS PHY
> nodes.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@xxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 70 ++++++++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index cde963c56ac9..491fffff8aa1 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -620,6 +620,76 @@ opp-202000000 {
> };
> };
>
> + ufs_mem_hc: ufshc@4804000 {
> + compatible = "qcom,sm6115-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
> + reg-names = "std", "ice";
I could imagine that testing DTS against existing bindings might miss a
lot, because we have still a lot of errors. But at least I would expect
you test your DTS against your own bindings, which you submit here (and
previously).
You just wrote that ice is not allowed.
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy_lanes>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <1>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> + iommus = <&apps_smmu 0x100 0>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
> + <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "core_clk_ice",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk";
> +
> + freq-table-hz = <50000000 200000000>,
> + <0 0>,
> + <0 0>,
> + <37500000 150000000>,
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> +
> + non-removable;
Is it allowed property?
> + status = "disabled";
> + };
> +
> + ufs_mem_phy: phy@4807000 {
> + compatible = "qcom,sm6115-qmp-ufs-phy";
> + reg = <0x4807000 0x1c4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_UFS_CLKREF_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> + clock-names = "ref", "ref_aux";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: lanes@4807400 {
> + reg = <0x4807400 0x098>,
> + <0x4807600 0x130>,
> + <0x4807c00 0x16c>;
> + #phy-cells = <0>;
> + };
> + };
> +
> +
Just one blank line.
Best regards,
Krzysztof
