TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
---
.../mfd/ti,j721e-system-controller.yaml | 6 ++++
.../bindings/phy/ti,phy-gmii-sel.yaml | 30 ++++++++++++++++++-
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 1aeac43cad92..802374e7645f 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -54,6 +54,12 @@ patternProperties:
description:
Clock provider for TI EHRPWM nodes.
+ "phy@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/phy/phy-provider.yaml
+ description:
+ This is the register to set phy mode through phy-gmii-sel driver.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index ff8a6d9eb153..0ffb97f1a77c 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -53,12 +53,24 @@ properties:
- ti,am43xx-phy-gmii-sel
- ti,dm814-phy-gmii-sel
- ti,am654-phy-gmii-sel
+ - ti,j7200-cpsw5g-phy-gmii-sel
reg:
maxItems: 1
'#phy-cells': true
+ ti,qsgmii-main-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Required only for QSGMII mode. Array to select the port for
+ QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
+ ports automatically. Any one of the 4 CPSW5G ports can act as the
+ main port with the rest of them being the QSGMII_SUB ports.
+ items:
+ minimum: 1
+ maximum: 4
+
allOf:
- if:
properties:
@@ -73,6 +85,22 @@ allOf:
'#phy-cells':
const: 1
description: CPSW port number (starting from 1)
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,j7200-cpsw5g-phy-gmii-sel
+ then:
+ properties:
+ '#phy-cells':
+ const: 1
+ description: CPSW port number (starting from 1)
+ ti,qsgmii-main-ports:
+ maxItems: 1
+ else:
+ properties:
+ ti,qsgmii-main-ports: false
- if:
properties:
compatible:
@@ -97,7 +125,7 @@ additionalProperties: false
examples:
- |
- phy_gmii_sel: phy-gmii-sel@650 {
+ phy_gmii_sel: phy@650 {
compatible = "ti,am3352-phy-gmii-sel";
reg = <0x650 0x4>;
#phy-cells = <2>;
--
2.25.1
