On Mon, 22 Aug 2022 21:46:55 +0300, Serge Semin wrote: > Baikal-T1 SoC is equipped with DWC PCIe v4.60a Root Port controller, which > link can be trained to work on up to Gen.3 speed over up to x4 lanes. The > controller is supposed to be fed up with four clock sources: DBI > peripheral clock, AXI application Tx/Rx clocks and external PHY/core > reference clock generating the 100MHz signal. In addition to that the > platform provide a way to reset each part of the controller: > sticky/non-sticky bits, host controller core, PIPE interface, PCS/PHY and > Hot/Power reset signal. The Root Port controller is equipped with multiple > IRQ lines like MSI, system AER, PME, HP, Bandwidth change, Link > equalization request and eDMA ones. The registers space is accessed over > the DBI interface. There can be no more than four inbound or outbound iATU > windows configured. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > > --- > > Changelog v2: > - Rename 'syscon' property to 'baikal,bt1-syscon'. > - Fix the 'compatible' property definition to being more specific about > what strings are supposed to be used. Due to that we had to add the > select property to evaluate the schema against the Baikal-T1 PCIe DT > nodes only. > > Changelog v5: > - Drop generic fallback names from the compatible property constraints. > (@Rob) > - Define ordered {reg,interrupt,clock,reset}-names properties. (@Rob) > - Drop minItems from the clocks and reset properties, since it equals > to the maxItems for them. > - Drop num-ob-windows and num-ib-windows properties constraint. (@Rob) > --- > .../bindings/pci/baikal,bt1-pcie.yaml | 153 ++++++++++++++++++ > 1 file changed, 153 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>