From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
On Thu, 25 Aug 2022 19:04:16 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> Whilst re-running checks before sending my dt-fixes PR today I noticed
> that I had introduced another dtbs_check warning by applying one of the
> patches in it.
>
> PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts
> re-uses the compatible of currently) which only has 3. Add a new string
> to the binding like should've been done in the first place...
>
> [...]
@Palmer, I have applied these to my dt-fixes, branch as the commit they
fix is there too. As I mentioned on IRC, patches for this dt-binding are
usually merged via the riscv tree so I have taken the liberty of bundling
it with the dts change. You may get this in a PR friday morning, but more
likely early next week.
Conor.
[1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
https://git.kernel.org/conor/c/17e4732d1d8a
[2/2] riscv: dts: microchip: use an mpfs specific l2 compatible
https://git.kernel.org/conor/c/0dec364ffeb6
Thanks,
Conor.
