RE: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



[AMD Official Use Only - General]



> -----Original Message-----
> From: Jason Gunthorpe <jgg@xxxxxxxxxx>
> Sent: Friday, August 26, 2022 5:38 AM
> To: Robin Murphy <robin.murphy@xxxxxxx>
> Cc: Saravana Kannan <saravanak@xxxxxxxxxx>; Greg KH
> <gregkh@xxxxxxxxxxxxxxxxxxx>; Gupta, Nipun <Nipun.Gupta@xxxxxxx>;
> robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; rafael@xxxxxxxxxx;
> eric.auger@xxxxxxxxxx; alex.williamson@xxxxxxxxxx; cohuck@xxxxxxxxxx;
> Gupta, Puneet (DCG-ENG) <puneet.gupta@xxxxxxx>;
> song.bao.hua@xxxxxxxxxxxxx; mchehab+huawei@xxxxxxxxxx; maz@xxxxxxxxxx;
> f.fainelli@xxxxxxxxx; jeffrey.l.hugo@xxxxxxxxx; Michael.Srba@xxxxxxxxx;
> mani@xxxxxxxxxx; yishaih@xxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; kvm@xxxxxxxxxxxxxxx; okaya@xxxxxxxxxx; Anand,
> Harpreet <harpreet.anand@xxxxxxx>; Agarwal, Nikhil
> <nikhil.agarwal@xxxxxxx>; Simek, Michal <michal.simek@xxxxxxx>; git
> (AMD-Xilinx) <git@xxxxxxx>
> Subject: Re: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver
> 
> [CAUTION: External Email]
> 
> On Thu, Aug 25, 2022 at 08:57:49PM +0100, Robin Murphy wrote:
> 
> > To my mind, it would definitely help to understand if this is a *real*
> > discoverable bus in hardware, i.e. does one have to configure one's device
> > with some sort of CDX wrapper at FPGA synthesis time, that then physically
> > communicates with some sort of CDX controller to identify itself once
> > loaded; or is it "discoverable" in the sense that there's some firmware on
> > an MCU controlling what gets loaded into the FPGA, and software can query
> > that and get back whatever precompiled DTB fragment came bundled with the
> > bitstream, i.e. it's really more like fpga-mgr in a fancy hat?
> 
> So much of the IP that you might want to put in a FPGA needs DT, I
> don't thing a simplistic AMBA like discoverable thing would be that
> interesting.
> 
> Think about things like FPGA GPIOs being configured as SPI/I2C, then
> describing the board config of SPI/I2C busses, setting up PCI bridges,
> flash storage controllers and all sorts of other typically embedded
> stuff that really relies on DT these days.
> 
> It would be nice if Xilinx could explain more about what environment
> this is targetting. Is it Zynq-like stuff?

This solution is not targeted for GPIO/SPI or I2C like devices which rely on
DT, but would have PCI like network/storage devices. It is not targeted for
Zynq platform. I have added more details on other mail. Please refer to
that mail.

Thanks,
Nipun

> 
> Jason




[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux