Add devicetree bindings support for SM8450 SoC. Only the clocks are
different on this platform, rest is same as SDX55.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 27 +++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 83a2cfc63bc1..9914d575ec41 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -12,6 +12,7 @@ maintainers:
properties:
compatible:
const: qcom,sdx55-pcie-ep
+ const: qcom,sm8450-pcie-ep
reg:
items:
@@ -33,11 +34,11 @@ properties:
clocks:
minItems: 7
- maxItems: 7
+ maxItems: 8
clock-names:
minItems: 7
- maxItems: 7
+ maxItems: 8
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
@@ -120,6 +121,28 @@ allOf:
- const: sleep # PCIe Sleep clock
- const: ref # PCIe Reference clock
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8450-pcie-ep
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: aux # PCIe Auxiliary clock
+ - const: cfg # PCIe CFG AHB clock
+ - const: bus_master # PCIe Master AXI clock
+ - const: bus_slave # PCIe Slave AXI clock
+ - const: slave_q2a # PCIe Slave Q2A AXI clock
+ - const: ref # PCIe Reference clock
+ - const: ddrss_sf_tbu # PCIe DDRSS SF TBU clock
+ - const: aggre_noc_axi # PCIe AGGRE NOC AXI clock
+
unevaluatedProperties: false
examples:
--
2.25.1
