Hi Samuel, On Fri 12 Aug 22, 02:55, Samuel Holland wrote: > A100 features an updated DPHY, which moves PLL control inside the DPHY > register space. (Previously PLL-MIPI was controlled from the CCU. This > does not affect the "clocks" property because the link between PLL-MIPI > and the DPHY was never represented in the devicetree.) It also requires > a modified analog power-on sequence. Finally, the new DPHY adds support > for operating as an LVDS PHY. D1 uses this same variant. Do you have some pointers about that? I'd be surprised that this PHY is now used for "traditional" LVDS display output, which is usually done with a simpler LVDS phy attached to the display controller. However I've seen that some new Allwinner SoCs come with sub-LVDS camera input, which typically requires a more complex PHY due to the high number of lanes. Anyway for now this is: Reviewed-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> Cheers, Paul > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> > --- > > .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > index cf49bd99b3e2..b88c4b52af7d 100644 > --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > @@ -17,9 +17,13 @@ properties: > compatible: > oneOf: > - const: allwinner,sun6i-a31-mipi-dphy > + - const: allwinner,sun50i-a100-mipi-dphy > - items: > - const: allwinner,sun50i-a64-mipi-dphy > - const: allwinner,sun6i-a31-mipi-dphy > + - items: > + - const: allwinner,sun20i-d1-mipi-dphy > + - const: allwinner,sun50i-a100-mipi-dphy > > reg: > maxItems: 1 > -- > 2.35.1 > -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com
Attachment:
signature.asc
Description: PGP signature
