Move schema for qcom,sdm845-mdss from dpu-sdm845.yaml to mdss.yaml so
that the dpu file describes only the DPU schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
.../bindings/display/msm/dpu-sdm845.yaml | 135 +++------
.../devicetree/bindings/display/msm/mdss.yaml | 265 ++++++++++++++----
2 files changed, 239 insertions(+), 161 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
index 2bb8896beffc..2074e954372f 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -10,139 +10,74 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@xxxxxxxxxxx>
description: |
- Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
- sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
- bindings of MDSS and DPU are mentioned for SDM845 target.
+ Device tree bindings for the DPU display controller for SDM845 target.
properties:
compatible:
items:
- - const: qcom,sdm845-mdss
+ - const: qcom,sdm845-dpu
reg:
- maxItems: 1
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
+ items:
+ - const: mdp
+ - const: vbif
clocks:
items:
- - description: Display AHB clock from gcc
+ - description: Display ahb clock
+ - description: Display axi clock
- description: Display core clock
+ - description: Display vsync clock
clock-names:
items:
- const: iface
+ - const: bus
- const: core
+ - const: vsync
interrupts:
maxItems: 1
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
- iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
-
- ranges: true
-
- resets:
- items:
- - description: MDSS_CORE reset
+ power-domains:
+ maxItems: 1
-patternProperties:
- "^display-controller@[0-9a-f]+$":
- type: object
- description: Node containing the properties of DPU.
+ operating-points-v2: true
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
properties:
- compatible:
- items:
- - const: qcom,sdm845-dpu
-
- reg:
- items:
- - description: Address offset and size for mdp register set
- - description: Address offset and size for vbif register set
-
- reg-names:
- items:
- - const: mdp
- - const: vbif
-
- clocks:
- items:
- - description: Display ahb clock
- - description: Display axi clock
- - description: Display core clock
- - description: Display vsync clock
-
- clock-names:
- items:
- - const: iface
- - const: bus
- - const: core
- - const: vsync
-
- interrupts:
- maxItems: 1
-
- power-domains:
- maxItems: 1
-
- operating-points-v2: true
- ports:
- $ref: /schemas/graph.yaml#/properties/ports
- description: |
- Contains the list of output ports from DPU device. These ports
- connect to interfaces that are external to the DPU hardware,
- such as DSI, DP etc. Each output port contains an endpoint that
- describes how it is connected to an external interface.
-
- properties:
- port@0:
- $ref: /schemas/graph.yaml#/properties/port
- description: DPU_INTF1 (DSI1)
-
- port@1:
- $ref: /schemas/graph.yaml#/properties/port
- description: DPU_INTF2 (DSI2)
-
- required:
- - port@0
- - port@1
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF1 (DSI1)
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF2 (DSI2)
required:
- - compatible
- - reg
- - reg-names
- - clocks
- - interrupts
- - power-domains
- - operating-points-v2
- - ports
+ - port@0
+ - port@1
required:
- compatible
- reg
- reg-names
- - power-domains
- clocks
- interrupts
- - interrupt-controller
- - iommus
- - ranges
+ - power-domains
+ - operating-points-v2
+ - ports
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml
index afc48d2b02f1..ef4709d87004 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml
@@ -18,17 +18,15 @@ properties:
compatible:
enum:
- qcom,mdss
+ - qcom,sdm845-mdss
reg:
- minItems: 2
+ minItems: 1
maxItems: 3
reg-names:
- minItems: 2
- items:
- - const: mdss_phys
- - const: vbif_phys
- - const: vbif_nrt_phys
+ minItems: 1
+ maxItems: 3
interrupts:
maxItems: 1
@@ -53,10 +51,10 @@ properties:
maxItems: 4
"#address-cells":
- const: 1
+ enum: [1, 2]
"#size-cells":
- const: 1
+ enum: [1, 2]
ranges:
true
@@ -65,29 +63,178 @@ properties:
items:
- description: MDSS_CORE reset
-oneOf:
- - properties:
- clocks:
- minItems: 3
- maxItems: 4
-
- clock-names:
- minItems: 3
- items:
- - const: iface
- - const: bus
- - const: vsync
- - const: core
- - properties:
- clocks:
- minItems: 1
- maxItems: 2
-
- clock-names:
- minItems: 1
- items:
- - const: iface
- - const: core
+ interconnects:
+ minItems: 2
+ items:
+ - description: MDP port 0
+ - description: MDP port 1
+ - description: Rotator
+
+ interconnect-names:
+ minItems: 2
+ items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+ - const: rotator-mem
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,mdss
+ then:
+ properties:
+ reg-names:
+ minItems: 2
+ items:
+ - const: mdss_phys
+ - const: vbif_phys
+ - const: vbif_nrt_phys
+ oneOf:
+ - properties:
+ clocks:
+ minItems: 3
+ maxItems: 4
+
+ clock-names:
+ minItems: 3
+ items:
+ - const: iface
+ - const: bus
+ - const: vsync
+ - const: core
+ - properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: iface
+ - const: core
+ else:
+ properties:
+ regs:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: mdss
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+ required:
+ - iommus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm845-mdss
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+
+ iommus:
+ minItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,mdss
+ then:
+ patternProperties:
+ "^mdp@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,mdp5
+
+ "^dsi@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,mdss-dsi-ctrl
+
+ "^dsi-phy@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - qcom,dsi-phy-14nm
+ - qcom,dsi-phy-14nm-660
+ - qcom,dsi-phy-20nm
+ - qcom,dsi-phy-28nm-hpm
+ - qcom,dsi-phy-28nm-lp
+
+ "^hdmi-phy@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - qcom,hdmi-phy-8084
+ - qcom,hdmi-phy-8660
+ - qcom,hdmi-phy-8960
+ - qcom,hdmi-phy-8974
+ - qcom,hdmi-phy-8996
+
+ "^hdmi-tx@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - qcom,hdmi-tx-8084
+ - qcom,hdmi-tx-8660
+ - qcom,hdmi-tx-8960
+ - qcom,hdmi-tx-8974
+ - qcom,hdmi-tx-8994
+ - qcom,hdmi-tx-8996
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm845-mdss
+ then:
+ patternProperties:
+ "^display-controller@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sdm845-dpu
+
+ "^dsi@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,mdss-dsi-ctrl
+
+ "^dsi-phy@[1-9a-f][0-9a-f]*$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - qcom,dsi-phy-10nm
required:
- compatible
@@ -106,48 +253,21 @@ required:
patternProperties:
"^mdp@[1-9a-f][0-9a-f]*$":
type: object
- properties:
- compatible:
- const: qcom,mdp5
+
+ "^display-controller@[1-9a-f][0-9a-f]*$":
+ type: object
"^dsi@[1-9a-f][0-9a-f]*$":
type: object
- properties:
- compatible:
- const: qcom,mdss-dsi-ctrl
"^dsi-phy@[1-9a-f][0-9a-f]*$":
type: object
- properties:
- compatible:
- enum:
- - qcom,dsi-phy-14nm
- - qcom,dsi-phy-20nm
- - qcom,dsi-phy-28nm-hpm
- - qcom,dsi-phy-28nm-lp
"^hdmi-phy@[1-9a-f][0-9a-f]*$":
type: object
- properties:
- compatible:
- enum:
- - qcom,hdmi-phy-8084
- - qcom,hdmi-phy-8660
- - qcom,hdmi-phy-8960
- - qcom,hdmi-phy-8974
- - qcom,hdmi-phy-8996
"^hdmi-tx@[1-9a-f][0-9a-f]*$":
type: object
- properties:
- compatible:
- enum:
- - qcom,hdmi-tx-8084
- - qcom,hdmi-tx-8660
- - qcom,hdmi-tx-8960
- - qcom,hdmi-tx-8974
- - qcom,hdmi-tx-8994
- - qcom,hdmi-tx-8996
additionalProperties: false
@@ -180,4 +300,27 @@ examples:
ranges;
};
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ display-subsystem@ae00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,sdm845-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc 19>,
+ <&dispcc 12>;
+ clock-names = "iface", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x880 0x8>,
+ <&apps_smmu 0xc80 0x8>;
+ ranges;
+ };
...
--
2.35.1
