On 19/08/2022 15:22, Conor Dooley wrote:
> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> ordinal corners of the chip, which our documentation refers to as
> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> highly configurable & many of the input clocks are optional.
>
Thank you for your patch. There is something to discuss/improve.
> + '#clock-cells':
> + const: 1
> + description: |
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell.
> + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
> + PolarFire clock IDs.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + ccc_nw: cccnwclk@38100000 {
Node names should be generic: clock-controller
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Best regards,
Krzysztof
