On 18/08/2022 18:18, Adam Skladowski wrote: > Add device tree bindings for display clock controller for > Qualcomm Technology Inc's SM6115 SoC. > > Signed-off-by: Adam Skladowski <a39.skl@xxxxxxxxx> > --- > .../bindings/clock/qcom,dispcc-sm6115.yaml | 88 +++++++++++++++++++ > .../dt-bindings/clock/qcom,dispcc-sm6115.h | 36 ++++++++ > 2 files changed, 124 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6115.yaml > create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6115.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6115.yaml > new file mode 100644 > index 000000000000..2b9671112934 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6115.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6115.yaml# Filename based on compatible, so: qcom,sm6115-dispcc.yaml I know it creates irregularity, but that's the naming convention for all. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display Clock Controller Binding for SM6115 > + > +maintainers: > + - Taniya Das <tdas@xxxxxxxxxxxxxx> I don't think the email is correct. Please use Bjorn's (and optionally you can add yourself if you want to maintain this binding). > + > +description: | > + Qualcomm display clock control module which supports the clocks and > + power domains on SM6115. > + > + See also: > + dt-bindings/clock/qcom,dispcc-sm6115.h > + > +properties: > + compatible: > + enum: > + - qcom,sm6115-dispcc > + > + clocks: > + items: > + - description: Board XO source > + - description: Byte clock from DSI PHY0 > + - description: Pixel clock from DSI PHY0 > + - description: GPLL0 clock from GCC > + - description: GPLL0 div clock from GCC > + - description: Board sleep clock > + > + clock-names: > + items: > + - const: bi_tcxo > + - const: dsi0_phy_pll_out_byteclk > + - const: dsi0_phy_pll_out_dsiclk > + - const: gcc_disp_gpll0_clk_src > + - const: gcc_disp_gpll0_div_clk_src > + - const: sleep_clk > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,rpmcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + clock-controller@5f00000 { > + compatible = "qcom,sm6115-dispcc"; > + reg = <0x5f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&dsi0_phy 0>, > + <&dsi0_phy 1>, > + <&gcc GCC_DISP_GPLL0_CLK_SRC>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, > + <&sleep_clk>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "gcc_disp_gpll0_clk_src", > + "gcc_disp_gpll0_div_clk_src", > + "sleep_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6115.h b/include/dt-bindings/clock/qcom,dispcc-sm6115.h > new file mode 100644 > index 000000000000..d1a6c45b5029 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,dispcc-sm6115.h Filename based on compatible. > @@ -0,0 +1,36 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2022, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H > +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H > + Best regards, Krzysztof
