Hello Rob, On 18/08/22 20:13, Rob Herring wrote: > On Tue, Aug 16, 2022 at 11:28:47AM +0530, Siddharth Vadapalli wrote: >> TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII >> that are not supported on earlier SoCs. Add a compatible for it. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> >> --- >> .../mfd/ti,j721e-system-controller.yaml | 5 ++++ >> .../bindings/phy/ti,phy-gmii-sel.yaml | 27 ++++++++++++++++++- >> 2 files changed, 31 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml >> index 73cffc45e056..527fd47b648b 100644 >> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml >> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml >> @@ -54,6 +54,11 @@ patternProperties: >> description: >> Clock provider for TI EHRPWM nodes. >> >> + "phy@[0-9a-f]+$": >> + type: object >> + description: >> + This is the register to set phy mode through phy-gmii-sel driver. > > No properties for this node? A whole node for 1 register? > > Or this node is ti,phy-gmii-sel.yaml? If so, add a $ref to it. Thank you for reviewing the patch. Yes, the node is for ti,phy-gmii-sel.yaml. I will add the $ref for it. > >> + >> required: >> - compatible >> - reg >> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml >> index ff8a6d9eb153..54da408d0360 100644 >> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml >> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml >> @@ -53,12 +53,21 @@ properties: >> - ti,am43xx-phy-gmii-sel >> - ti,dm814-phy-gmii-sel >> - ti,am654-phy-gmii-sel >> + - ti,j7200-cpsw5g-phy-gmii-sel >> >> reg: >> maxItems: 1 >> >> '#phy-cells': true >> >> + ti,qsgmii-main-ports: >> + $ref: /schemas/types.yaml#/definitions/uint32-array >> + description: | >> + Required only for QSGMII mode. Array to select the port for >> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB >> + ports automatically. Any one of the 4 CPSW5G ports can act as the >> + main port with the rest of them being the QSGMII_SUB ports. > > Constraints? This is an optional property that should only be used for the ti,j7200-cpsw5g-phy-gmii-sel compatible if it is used. I did not realize that by defining it here, I had automatically defined it as a valid property for all the compatibles. I will restrict this property only to the ti,j7200-cpsw5g-phy-gmii-sel compatible by extending the if-then statement below, adding an else statement with "ti,qsgmii-main-ports: false", which will disallow this property for other compatibles. > >> + >> allOf: >> - if: >> properties: >> @@ -73,6 +82,22 @@ allOf: >> '#phy-cells': >> const: 1 >> description: CPSW port number (starting from 1) >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - ti,j7200-cpsw5g-phy-gmii-sel >> + then: >> + properties: >> + '#phy-cells': >> + const: 1 >> + description: CPSW port number (starting from 1) >> + ti,qsgmii-main-ports: >> + maxItems: 1 > > An array, but only 1 entry allowed? For the ti,j7200-cpsw5g-phy-gmii-sel compatible, only one entry is allowed, but in the future, I will be adding a new compatible which will require two entries for the ti,qsgmii-main-ports property. On TI's J721e device, there are a total of 8 external ports, therefore making it possible to configure them as two sets of QSGMII interfaces. This requires two qsgmii-main ports which can be specified in the ti,qsgmii-main-ports property as an array. Therefore, I have declared the property as an array. > >> + items: >> + minimum: 1 >> + maximum: 4 > > Can't this be up above? Yes, I will move it to the top where the ti,qsgmii-main-ports property is defined. Regards, Siddharth.
