> -static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg)
> +static irqreturn_t mvebu_pcie_error_irq_handler(int irq, void *arg)
> +{
> + struct mvebu_pcie_port *port = arg;
> + struct device *dev = &port->pcie->pdev->dev;
> + u32 cause, unmask, status;
> +
> + cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF);
> + unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
> + status = cause & unmask;
> +
> + /* "error" interrupt handler does not process INTX interrupts */
> + status &= ~(PCIE_INT_INTX(0) | PCIE_INT_INTX(1) |
> + PCIE_INT_INTX(2) | PCIE_INT_INTX(3));
Just for my understanding...
There are two interrupts, but the status information what those
interrupts actually mean are all packed into one register? I assume
reading the clause register does not clear set bits? Otherwise there
would be a race condition. Are these actually level interrupts, and in
order to clear them you need to poke some other register?
> + /*
> + * Old DT bindings do not contain "error" interrupt
> + * so do not fail probing driver when interrupt does not exist.
> + */
> + port->error_irq = of_irq_get_byname(child, "error");
> + if (port->error_irq == -EPROBE_DEFER) {
> + ret = port->error_irq;
> + goto err;
> + }
> + if (port->error_irq <= 0) {
> + dev_warn(dev, "%s: interrupts on Root Port are unsupported, "
Maybe that should be "Error interrupts on Root..." ?
Andrew
