This patch series add DTS node, dt-bindings document and driver for memory controller present on Nuvoton NPCM SoCs. The memory controller supports single bit error correction and double bit error detection (in-line ECC in which a section 1/8th of the memory device used to store data is used for ECC storage). Marvin Lin (3): arm: dts: nuvoton: Add node for NPCM memory controller dt-bindings: edac: nuvoton: Add document for NPCM memory controller EDAC/nuvoton: Add NPCM memory controller driver .../edac/nuvoton,npcm-memory-controller.yaml | 54 ++ MAINTAINERS | 7 + arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 + drivers/edac/Kconfig | 11 + drivers/edac/Makefile | 1 + drivers/edac/npcm_edac.c | 512 ++++++++++++++++++ 6 files changed, 592 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml create mode 100644 drivers/edac/npcm_edac.c -- 2.17.1
