Quoting Bjorn Andersson (2022-08-10 21:28:55)
> diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c
> new file mode 100644
> index 000000000000..555fd4ff58ab
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-sc8280xp.c
> @@ -0,0 +1,460 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
include kernel.h for ARRAY_SIZE please.
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> + DT_BI_TCXO,
> + DT_GCC_GPU_GPLL0_CLK_SRC,
> + DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
> +};
> +
> +enum {
> + P_BI_TCXO,
> + P_GCC_GPU_GPLL0_CLK_SRC,
> + P_GCC_GPU_GPLL0_DIV_CLK_SRC,
> + P_GPU_CC_PLL0_OUT_MAIN,
> + P_GPU_CC_PLL1_OUT_MAIN,
> +};
> +
> +static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
> +
> +static const struct pll_vco lucid_5lpe_vco[] = {
> + { 249600000, 1800000000, 0 },
> +};
> +
> +static struct alpha_pll_config gpu_cc_pll0_config = {
> + .l = 0x1c,
> + .alpha = 0xa555,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00002261,
> + .config_ctl_hi1_val = 0x2a9a699c,
> + .test_ctl_val = 0x00000000,
> + .test_ctl_hi_val = 0x00000000,
> + .test_ctl_hi1_val = 0x01800000,
> + .user_ctl_val = 0x00000000,
> + .user_ctl_hi_val = 0x00000805,
> + .user_ctl_hi1_val = 0x00000000,
> +};
> +
> +static struct clk_alpha_pll gpu_cc_pll0 = {
> + .offset = 0x0,
> + .vco_table = lucid_5lpe_vco,
> + .num_vco = ARRAY_SIZE(lucid_5lpe_vco),
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
const?
> + .name = "gpu_cc_pll0",
> + .parent_data = &parent_data_tcxo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_lucid_5lpe_ops,
> + },
> + },
> +};
