From: Peng Fan <peng.fan@xxxxxxx> V2: Add A-b from Rob Add a new patch 2 reported by intel test robot Use Abel's new address for sending mail The current clk driver use gate API as i.MX8M*, the gate2 API use 0x3 as val/mask, however i.MX93 LPCG DIRECT use BIT0 as on/off gate. So clk disable unused actually not gate off the LPCG clocks. And i.MX93 has AUTHEN feature, so add a new API to support i.MX93 clk gate. i.MX93 CCM ROOT has slice busy check bit when updating register value, add check. CCM ROOT also has AUTHEN whitelist, so add DID check. Besides the gate/composite update, add MU[X] and SAI IPG clk in this patchset This patchset has got reviewed in NXP internal, so I keep R-b tag here. For those that have some change compared with downstream, R-b tag dropped. Peng Fan (8): dt-bindings: clock: imx93-clock: add more MU/SAI clocks clk: imx93: guard imx93_clk_of_match with CONFIG_OF clk: imx: clk-composite-93: check slice busy clk: imx: clk-composite-93: check white_list clk: imx: add i.MX93 clk gate clk: imx93: switch to use new clk gate API clk: imx93: add MU1/2 clock clk: imx93: add SAI IPG clk drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-composite-93.c | 171 +++++++++++++++++++- drivers/clk/imx/clk-gate-93.c | 199 ++++++++++++++++++++++++ drivers/clk/imx/clk-imx93.c | 32 ++-- drivers/clk/imx/clk.h | 9 +- include/dt-bindings/clock/imx93-clock.h | 9 +- 6 files changed, 403 insertions(+), 19 deletions(-) create mode 100644 drivers/clk/imx/clk-gate-93.c -- 2.37.1
