Dear Krzysztof Thank you for your comments, I will revise it in the next edition. Thanks, Best regards, Garmin On Tue, 2022-08-02 at 09:31 +0200, Krzysztof Kozlowski wrote: > On 29/07/2022 10:24, Garmin.Chang wrote: > > Add the new binding documentation for system clock > > and functional clock on MediaTek MT8188. > > > > Signed-off-by: Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx> > > --- > > .../arm/mediatek/mediatek,mt8188-clock.yaml | 230 ++++++ > > .../mediatek/mediatek,mt8188-sys-clock.yaml | 75 ++ > > include/dt-bindings/clock/mt8188-clk.h | 759 > > ++++++++++++++++++ > > 3 files changed, 1064 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188-sys- > > clock.yaml > > create mode 100644 include/dt-bindings/clock/mt8188-clk.h > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > new file mode 100644 > > index 000000000000..b03745fe971a > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > clock.yaml > > @@ -0,0 +1,230 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: " > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!ydPMfABiSHOE2O88pjxcZhMrkJ-Scd1BPzPWaC6BmRz3-mjqJZxOOr8G8cl2alHGbUg$ > > " > > +$schema: " > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!ydPMfABiSHOE2O88pjxcZhMrkJ-Scd1BPzPWaC6BmRz3-mjqJZxOOr8G8cl2tjHoC30$ > > " > > No need for quotes. > > > + > > +title: MediaTek Functional Clock Controller for MT8188 > > + > > +maintainers: > > + - Garmin Chang <garmin.chang@xxxxxxxxxxxx> > > + > > +description: | > > + The clock architecture in MediaTek like below > > + PLLs --> > > + dividers --> > > + muxes > > + --> > > + clock gate > > + > > + The devices provide clock gate control in different IP blocks. > > + > > +properties: > > + compatible: > > + items: > > You have just one item, so no "items". > > > + - enum: > > + - mediatek,mt8188-imp_iic_wrap_c > > + - mediatek,mt8188-imp_iic_wrap_en > > + - mediatek,mt8188-imp_iic_wrap_w > > + - mediatek,mt8188-mfgcfg > > + - mediatek,mt8188-vppsys0 > > + - mediatek,mt8188-wpesys > > + - mediatek,mt8188-wpesys_vpp0 > > + - mediatek,mt8188-vppsys1 > > + - mediatek,mt8188-imgsys > > + - mediatek,mt8188-imgsys_wpe1 > > + - mediatek,mt8188-imgsys_wpe2 > > + - mediatek,mt8188-imgsys_wpe3 > > + - mediatek,mt8188-imgsys1_dip_top > > + - mediatek,mt8188-imgsys1_dip_nr > > + - mediatek,mt8188-ipesys > > + - mediatek,mt8188-camsys > > + - mediatek,mt8188-camsys_rawa > > + - mediatek,mt8188-camsys_yuva > > + - mediatek,mt8188-camsys_rawb > > + - mediatek,mt8188-camsys_yuvb > > + - mediatek,mt8188-ccusys > > + - mediatek,mt8188-vdecsys_soc > > + - mediatek,mt8188-vdecsys > > + - mediatek,mt8188-vencsys > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > clock-cells should be required as well. > > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + imp_iic_wrap_c: clock-controller@11283000 { > > + compatible = "mediatek,mt8188-imp_iic_wrap_c"; > > + reg = <0x11283000 0x1000>; > > + #clock-cells = <1>; > > + }; > > > Only one example is enough. All others are exactly the same. > > > + > > + - | > > + imp_iic_wrap_en: clock-controller@11ec2000 { > > + compatible = "mediatek,mt8188-imp_iic_wrap_en"; > > + reg = <0x11ec2000 0x1000>; > > + #clock-cells = <1>; > > + }; > > > > + > > + - | > > + imp_iic_wrap_w: clock-controller@11e02000 { > > + compatible = "mediatek,mt8188-imp_iic_wrap_w"; > > + reg = <0x11e02000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + mfgcfg: clock-controller@13fbf000 { > > + compatible = "mediatek,mt8188-mfgcfg"; > > + reg = <0x13fbf000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + vppsys0: clock-controller@14000000 { > > + compatible = "mediatek,mt8188-vppsys0"; > > + reg = <0x14000000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + wpesys: clock-controller@14e00000 { > > + compatible = "mediatek,mt8188-wpesys"; > > + reg = <0x14e00000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + wpesys_vpp0: clock-controller@14e02000 { > > + compatible = "mediatek,mt8188-wpesys_vpp0"; > > + reg = <0x14e02000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + vppsys1: clock-controller@14f00000 { > > + compatible = "mediatek,mt8188-vppsys1"; > > + reg = <0x14f00000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + imgsys: clock-controller@15000000 { > > + compatible = "mediatek,mt8188-imgsys"; > > + reg = <0x15000000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + imgsys_wpe1: clock-controller@15220000 { > > + compatible = "mediatek,mt8188-imgsys_wpe1"; > > + reg = <0x15220000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + imgsys_wpe2: clock-controller@15520000 { > > + compatible = "mediatek,mt8188-imgsys_wpe2"; > > + reg = <0x15520000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + imgsys_wpe3: clock-controller@15620000 { > > + compatible = "mediatek,mt8188-imgsys_wpe3"; > > + reg = <0x15620000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + imgsys1_dip_top: clock-controller@15110000 { > > + compatible = "mediatek,mt8188-imgsys1_dip_top"; > > + reg = <0x15110000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + imgsys1_dip_nr: clock-controller@15130000 { > > + compatible = "mediatek,mt8188-imgsys1_dip_nr"; > > + reg = <0x15130000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + ipesys: clock-controller@15330000 { > > + compatible = "mediatek,mt8188-ipesys"; > > + reg = <0x15330000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + camsys: clock-controller@16000000 { > > + compatible = "mediatek,mt8188-camsys"; > > + reg = <0x16000000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + camsys_rawa: clock-controller@1604f000 { > > + compatible = "mediatek,mt8188-camsys_rawa"; > > + reg = <0x1604f000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + camsys_yuva: clock-controller@1606f000 { > > + compatible = "mediatek,mt8188-camsys_yuva"; > > + reg = <0x1606f000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + camsys_rawb: clock-controller@1608f000 { > > + compatible = "mediatek,mt8188-camsys_rawb"; > > + reg = <0x1608f000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + camsys_yuvb: clock-controller@160af000 { > > + compatible = "mediatek,mt8188-camsys_yuvb"; > > + reg = <0x160af000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + ccusys: clock-controller@17200000 { > > + compatible = "mediatek,mt8188-ccusys"; > > + reg = <0x17200000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + vdecsys_soc: clock-controller@1800f000 { > > + compatible = "mediatek,mt8188-vdecsys_soc"; > > + reg = <0x1800f000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + vdecsys: clock-controller@1802f000 { > > + compatible = "mediatek,mt8188-vdecsys"; > > + reg = <0x1802f000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + vencsys: clock-controller@1a000000 { > > + compatible = "mediatek,mt8188-vencsys"; > > + reg = <0x1a000000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > new file mode 100644 > > index 000000000000..b97cad03241c > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8188- > > sys-clock.yaml > > @@ -0,0 +1,75 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: " > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!ydPMfABiSHOE2O88pjxcZhMrkJ-Scd1BPzPWaC6BmRz3-mjqJZxOOr8G8cl21roH3SU$ > > " > > +$schema: " > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!ydPMfABiSHOE2O88pjxcZhMrkJ-Scd1BPzPWaC6BmRz3-mjqJZxOOr8G8cl2tjHoC30$ > > " > > All previous comments apply here and further as well. > > (...) > > > diff --git a/include/dt-bindings/clock/mt8188-clk.h b/include/dt- > > bindings/clock/mt8188-clk.h > > new file mode 100644 > > index 000000000000..bd1f21bd6584 > > --- /dev/null > > +++ b/include/dt-bindings/clock/mt8188-clk.h > > Filename with vendor prefix, so "mediatek,mt8188-clk.h" > > > Best regards, > Krzysztof
